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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

FPGA-to-HPS bridge data width on Agilex-7 M-series

Hello

I'm working with Agilex 7 AGM039 device and in platform designer I see that data width of FPGA-to-HPS bridge has only 2 valid options: 128b and 256b, while with Agilex 7 I-series it has 512b option(FPGA-to-HPS Bridge). Also in documentation for Agilex 7 HPS I didn't find any mentions that data width doesn't have 512b option.

So my question is whether it is an undocumented feature or there is something wrong with my Quartus?

Quartus version is 23.4 and Platform Designer 23.4 Build 79.

Fpga Devkit
  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    2 years ago

    Hi,


    From our factory team, the Agilex 7 M-series is 128/256 bit.


    We will update our documentation on this info.


6 Replies

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Allow me sometime to double check with our internal team on that settings for Agilex 7 M-series.


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    From our factory team, the Agilex 7 M-series is 128/256 bit.


    We will update our documentation on this info.


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



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