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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

FPGA-to-HPS bridge data width on Agilex-7 M-series

Hello I'm working with Agilex 7 AGM039 device and in platform designer I see that data width of FPGA-to-HPS bridge has only 2 valid options: 128b and 256b, while with Agilex 7 I-series it has 512b o...
Fpga Devkit
  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    2 years ago

    Hi,


    From our factory team, the Agilex 7 M-series is 128/256 bit.


    We will update our documentation on this info.


EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Allow me sometime to double check with our internal team on that settings for Agilex 7 M-series.