Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
The simplest way to do something like that is with a counter. Something like this maybe?
Obviously you could change the size of the counter, the polarity of the out signal, and the MAX_COUNT (which could even be another register if you want to change it during run time). The counter is essentially acting as the capacitor in this case, counting up (charging), until some threshold after which the output clears.localparam MAX_COUNT = 8'b1110; reg out; reg counter = MAX_COUNT; always @ (posedge clock) begin if (trigger) begin counter <= 8'b0; out <= 1'b1; //out is set on trigger end else if (counter != MAX_COUNT) begin counter <= counter + 8'b1; end else begin out <= 1'b0; // out is cleared after count end end - Altera_Forum
Honored Contributor
--- Quote Start --- The simplest way to do something like that is with a counter. Something like this maybe?
Obviously you could change the size of the counter, the polarity of the out signal, and the MAX_COUNT (which could even be another register if you want to change it during run time). The counter is essentially acting as the capacitor in this case, counting up (charging), until some threshold after which the output clears. --- Quote End --- Awesome thanks! I will definitely try out this design. I have been looking for a method that doesn't require a clock, but I think this might work. It just limits the "values" of the "capacitance" to# clock cycles, meaning it can't have a of 1.32124 clock cycles as the "charge time". Thoughts?localparam MAX_COUNT = 8'b1110; reg out; reg counter; always @ (posedge clock) begin if (trigger) begin counter <= 8'b0; out <= 1'b1; //out is set on trigger end else if (counter != MAX_COUNT) begin counter <= counter + 8'b1; end else begin out <= 1'b0; // out is cleared after count end end - Altera_Forum
Honored Contributor
You just have to make your clock fast enough for the resolution you want. For example a 100MHz clock would give you 10ns resolution - do you really need more than that for your project?
FPGAs like clocks, its what synchronises everything together. While it would be possible to replace (posedge clock) with *, I really wouldn't recommend it as who knows what would happen as it would be very likely that your counter would start developing funny glitches (if it works at all) as each bit of it may have slightly different propagation delays from another.