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Altera_Forum
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14 years ago

FPGA replace CPLD

I have a hdl program with several array such as [31:0] , [12:0] and [16:0] , only FPGA can holds such a large memory , one problem I faced is no NIOS II CPU is used and wish to remember the program a...
Altera_Forum's avatar
Altera_Forum
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14 years ago

you need an external flash memory, such an an EPCS, and connect if to the FPGA. Then store your design in the flash and the FPGA will be configured at power on.