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Altera_Forum's avatar
Altera_Forum
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13 years ago

FPGA remote upgrade question

Hello,

I'm designing a PCB with a Cyclone IV FPGA on it. It will connect to another board with a CPU via an SPI bus. I need to enable a remote upgrade of the FPGA image by the CPU. I read the Configuration and Remote System Upgrades in Cyclone IV Devices chapter in the handbook but I can't find a clear explanation regarding which FPGA pins are used for the remote upgrade process (from board design point of view).

The FPGA will be using a configuration device so actually I need to update the image on the device and not on the FPGA itself. What is the best way to do that?

Thanks in advance.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Is your configuration flash an EPCS chip? If yes then it is just a SPI flash, so you need to provide a way for your CPU to access it as an SPI device, or put your own SPI master IP in the FPGA, master that will be controlled by your CPU.

    The remote system upgrade component isn't used to change the contents of the configuration device, but just to trigger a reconfiguration request to the FPGA (i.e. ask the FPGA to load a new configuration from the flash).
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you for your help.

    Yes, I'll use an EPCS device.

    Just to make sure that I fully understand: The CPU will send the image to the FPGA (the FPGA being the SPI slave on that part) and the FPGA will transfer the image bits directly to the EPCS device (the FPGA being the SPI master)? The FPGA pins that are connected to the EPCS always can be used as GPIOs for that matter?

    Is there a specific address in the EPCS that I need to write the image to?

    After the new image is fully transferred to the EPCS how do I tell the FPGA to re-load the image?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    You probably need some logic on the FPGA that the SPI slave can modify in order to generate the SPI master cycles to the EPCS device.

    This probably requires multiple SPI requests from the originating CPU in order to generate a single request to the EPCS device.

    If you've set the FPGA's SPI slave so that it is able to generate arbitratrary Avalon master cycles (I don't know if there is a standard logic block for that!) then you can use that to drive the normal avalon slave SPI master interface (an SPI slave like that gives a lot of flexibility and can also make debugging easier as it allows dumps of the fgga state).

    The simplest thing is to overwrite the main image at the start of the EPCS device and then hard reset the board.

    If it all goes horribly wrong you have a 'return to factory' problem for the JTAG rewrite of the EPCS.

    There is an optional logic block that will allow a second image to be loaded under 'software' control - some recent threads talk aboit some issues with it (probably trying to boot nios cpus).
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    At first I thought that I should right 2 different blocks in the FPGA, the first is SPI slave that connects to the CPU and transfers the data to the second block, which is an SPI master that connects to the EPCS and writes the data.

    Now I thought of a better idea - actually I can wire the SPI bus from the CPU directly to the EPCS (by "wire" I mean in the FPGA) so that the CPU will write the EPCS with no additional logic in the FPGA, correct?

    In any case I don't need any additional GPIOs between the FPGA and the CPU except the ones used for SPI, right?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes you are right. But do you need any communication from the CPU to the FPGA on the SPI bus to other things than access to the EPCS? If not then your solution is the simplest, but if yes, you will need a mechanism to know when to switch the CPU SPI bus from your application to the EPCS and back again.

    To answer you other questions, the pins between the EPCS and the FPGA can be configured as regular I/O, so indeed you can do what you want with them in your application, including putting your own master or connecting directly the CPU's SPI bus to the EPCS. And to tell the FPGA to load the new image, you can either do it externally, with a hard reset as dsl said, or internally with the remote update IP.