Fpga_"PHY" to RJ45 with transformer

I don't claim to solve your problem from a distance, particularly as you didn't give much details on the pulse scheme and I/O settings at the FPGA side. But I simply assume, that you are using double push-pull drivers with a scheme as sketched above. Then, as said, "the center tap must be allowed to float". It's the same with integrated PHY controller chips like Davicom DM9008, they are known to fail in operation, if you connect a capacitor at the Tx center tap. True differential current source drivers in contrast have no problem with bypassing the center tap, or even require it.