Fpga_"PHY" to RJ45 with transformer

O.K., transmit only should be more easy. But without knowing how the connected pins are driven logically, I can't determine if something wrong with the circuit. I know Tx circuits of regular 10BASE-T PHYs, that also drive basically logic levels to the magnetics. They won't work correctly with a capacitor connected to the center tap, because it disturbs the output signal. The chip is e.g. driving "11" in idle state and "01" or "10" for positive or negative signal. To give correct output levels, the center tap must be allowed to float in this case. But your drive scheme is possibly different. I don't understand the purpose of the RL termination, that differs from usual ethernet circuits.

Of course, the problem may be caused by higher ethernet protocol layers as well. Before receiving packets, the peer (PC) should be able to detect a link.

But the best way is to check the generated output with an oscilloscope against ethernet signal specification. You said, you have watched the signal, you should try to find out if the waveform is correct.