FPGA PCB desing considerations

Hi,

I am currently working on a data acquisition system that includes an ADC, a SRAM memory chip and an FPGA. The main idea here is to sample the waveforms with the ADC, feed the data to the memory chip, then use the FPGA and some USB device to send the data from the memory chip to the FPGA and then to a PC for further processing. The ADC chip uses LVDS but the SRAM uses CMOS so I also have to use a translation IC between those to. I have two problems that have to do with the PCB design:

1) At first I want to send the digital data at 200 MHz from the ADC to SRAM. When this process is done, the data will be transferred at a much slower speed from the SRAM to the FPGA. The question is: Can I hardwire the SRAM data bus both to the ADC and the FPGA or this could cause damage (e.g. due to signal reflections) to any of the two devices when the SRAM communicates with the other? The translator I use has an Enable/Disable function which I can use to isolate the ADC when the SRAM sends the data to the FPGA, while I can use some tristate option for the FPGA I/O pins for the opposite situation.

2) Because LVDS is a source synchronous interface, the ADC also provides a synchronizing clock along with the data (also LVDS). In order to synchronize the data with the SRAM addressing I need to feed that clock to the FPGA. Is it possible to create some internal signal delay inside the FPGA in order to compensate for the delay inserted by the translation device (according to the datasheet, 2.6 ns), or is such compensation unachievable?

thanks in advance,

Lambros Gavriilides