FPGA or CPLD?

actually the default toggle rate of 12.5% is that of a 16 bit counter.

here is altera help:

Enter the average percentage of logic toggling on each clock cycle. The toggle percentage ranges

from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a

16-bit counter. To ensure you do not underestimate the toggle percentage, you can use a higher

toggle percentage. Most logic only toggles infrequently, and hence toggle rates of less than 50%

are more realistic