FPGA or CPLD?

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Hi Kaz,

thank you for responding to my post, I appreciate it. How would I estimate the power consumption of the operating CPLD?

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There is a tool "Power play power analysis" under processing menu.

It requires you first compile then run the tool either on a percent toggle rate or actual simulation data. The toggle rate may be enough if you enter the average.

clock is taken as 200%, half clock as 100%, 1/4 clock is 50% and so on. Each counter bit can thus be estimated then all averaged.