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4) The AS configuration circuit is the same as Fig. 8-3 in Cyclone IV configuration handbook. Two FPGAs share a single sof file.
(
http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf)
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Figure 8-3 shows a configuration scheme where the two FPGAs configure in sequence, i.e., there must be two files in the programming flash. They can be the exact same file, but there needs to be two of them. If you wanted the same file downloaded simultaneously, then you would need to have both chip-enables (nCE) grounded.
If you are loading the serial flash with just a single image, then that is the source of your issue.
Cheers,
Dave
Honored Contributor
