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Altera_Forum
Honored Contributor
13 years agoHi, Dave and fpgajeg
Sorry for my late reply. I was quite busy for other issues in the past few days. Let me redescribe my design about the FPGA configuration. 1) My design has two FPGAs. They are both Cyclone IV GX 50. 2) Each FPGA has a JTAG header, so there are two JTAG headers on my pcb. Two FPGAs are not in a JTAG chain. 3) There is another header for AS programming of a serial flash. The serial flash is not EPCS. (In summary, JTAG header 1 is for the first FPGA, JTAG header 2 is for the second FPGA, and the AS header is for the serial flash) 4) The AS configuration circuit is the same as Fig. 8-3 in Cyclone IV configuration handbook. Two FPGAs share a single sof file. (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf) 5) FPGAs can work if FPGAs are configured via the JTAG headers (using sof file). As fpgajeg said, I must configure the first FPGA then the second to make CONF_DONE signal high. 6) FPGAs cannot work no matter jic or pof is used. For jic file, I first configure each FPGA with a design for led blinking. After that, I write jic file to the serial flash via the first JTAG header. For pof file, I write pof file via the AS header. Hope my statement this time won't be confused anymore. ^^ For now, after I try to configure FPGA from serial flash and repower on the PCB, CONF_DONE is low and nStatus is high for a very short time (approx. 2 us), then goes low for a long time (approx. 110 us), and repeats the same pattern. (low, low, low, ..., low, high, low, low, low, ..., low, high, ...) Is this problem related to my adopted serial flash because I'm not using EPCS? Thanks.