Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHaving two JTAG headers (one for each FPGA) isn't a problem, just not necessary, and in this case leaves more room for error. Dave is right about the order that the FPGAs need to be configured -- until the nCE of an FPGA is low, the FPGA can't be configured. Also, if the CONF_DONE signals are tied together, neither FPGA will enter "user" mode until both have been configured (if by JTAG, you'd have to load the first, then the second).