Forum Discussion
New ContributorFPGA Initialization / Reset
Hi,
I have tried to search for information on how to manage FPGA initialization / reset and have not found conclusive information so I would appreciate some help on this topic.
- Is it a reset signal always necessary to initialize the FPGA to a known state? What can be done if there is no reset signal available?
- Can you know the initialization value of registers and state machines without using a reset signal?
- Can registers and finite state machines be initialized using VHDL / Verilog code?
Thank you in advance.
13 Replies
sstrellSuper Contributor
At the conclusion of programming of all devices (except Hyperflex devices; see below), all outputs are initialized low. So it's highly recommended to have a reset scheme to set things correctly. Depending on the way the design is written, initialized registers in code can go high, but this will be after everything starts low.
Hyperflex devices (Stratix 10, Agilex) do have the ability to have outputs initialized high from device programming so you may be able to get away without design reset, but it's still recommended to do it.
