FPGA Hard Memory Controller

I have been attempting to build a project that utilises the FPGA hard memory controller on the Cyclone V SoC using the SocKit development board.

A sample project is available on RocketBoards which uses the FPGA memory with a soft memory controller: http://www.rocketboards.org/foswiki/projects/sockitvideoipvipreferencedesign

In my project I have set up the soft memory controller in the same way and have successfully been able to access the FPGA memory via the HPS to write to FPGA memory locations (by opening "/dev/mem" and mapping the memory locations 0xC000 0000 to 0xFC00 0000). However, when I attempt to instantiate it as a hard memory controller and attempt the same HPS accesses, the HPS "hangs" (the terminal freezes and will not respond until a hard reset is asserted).

I have used the afi_clk as the clock signal for the avalon interface to the HPS component and connected the avl_0 port to h2f_axi_master on the HPS. The cmd, rd and write FIFO's are also clocked by afi_clk. I have also tried numerous configurations of other clocking schemes and settings on the memory controller, all having the same effect that the HPS freezes when I attempt to access the memory.

Has anyone successfully used the FPGA hard memory controller on the Cyclone V?