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Altera_Forum
Honored Contributor
Honored ContributorFPGA Hard Memory Controller
I have been attempting to build a project that utilises the FPGA hard memory controller on the Cyclone V SoC using the SocKit development board. A sample project is available on RocketBoards wh...
Altera_ForumHonored Contributor
Honored ContributorSee your other post that I replied to, I suspect the bridge isn't setup properly and causing accesses to block.
