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Altera_Forum's avatar
Altera_Forum
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12 years ago

FPGA GPIO voltage falling

Hi, as part of my final project for elecronic engineering, Ii have designed a 8051 based SoC with SPI master/slave interface. The problem I am facing is as followos: When I transmit SPI da...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi, thanks for the answer.

I did some "debug", and found out, the problem was caused by my BIDIR ports of the SPI slave (my design enables QSPI). once i defined the port as input only, the voltage was O.k.

after some more debug, i realized, that for some strange reason, the FSM read flag was raised => the inputs were turned over to output (thus explaining why the voltage fell after the first byte...).

this is very wierd since i sent a"write" command, and according to my test block, the command was accepted correctly by the slave.

do you have any idea how could a signal go high even though on simulation it didn't?