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Altera_Forum's avatar
Altera_Forum
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12 years ago

FPGA GPIO voltage falling

Hi, as part of my final project for elecronic engineering, Ii have designed a 8051 based SoC with SPI master/slave interface. The problem I am facing is as followos: When I transmit SPI da...
Altera_Forum's avatar
Altera_Forum
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12 years ago

This sounds like you have the signal directions wrong.

SPI devices often have pins with names like; selN, sck, sdi, and sdo. The port names "serial data in" and "serial data out" are ambiguous, since those names at the slave do not correspond to those same directions at the SPI master, so the industry has adopted the namng convention miso "master in/slave out" and mosi "master out/slave in".

I'd recommend checking that your FPGA output is connected to the SPI slave *input*.

Since you are seeing the voltage drop to ~half, I suspect you have the FPGA output driving the SPI slave output.

Cheers,

Dave