Forum Discussion

Gyud0's avatar
Gyud0
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

FPGA design that overloads the FPGA and varing it's power consumption

Hey, I'm looking for a FPGA design that overloads the FPGA and alter it's power consumption by a demanding (it can be configured by a generic ports). Do you know something about it? Thank you
Power
Gyud0's avatar
Gyud0
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hey again,

I mean that I need a design (or a guidance) that consumes a lot of ALMs and it makes the FPGA to consume more power.

And in the next level, I would like to control how many ALMs this design requires.

  • _AK6DN_'s avatar
    _AK6DN_
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Make a long shift register with multiple taps.

    Like really long, 100K to 250K bits, whatever you do to get to 75% or more utilization on your target device.

    Then feed an alternating 0/1 pattern into it, causing 100% activity on those logic paths.

    And maybe provide several intermediate points where you can force in a 0 or 1 to disable trailing cells, to allow tailoring your power consumption.

    And use a variable frequency master clock input as well to allow varying overall power consumption.