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Gyud0
Occasional Contributor
Occasional ContributorFPGA design that overloads the FPGA and varing it's power consumption
Hey, I'm looking for a FPGA design that overloads the FPGA and alter it's power consumption by a demanding (it can be configured by a generic ports). Do you know something about it? Thank you
FvM
Super Contributor
Super ContributorHi,
not clear what you mean with overload? You can generate a test design with maximal core current consumption by clocking many ("all") logic cells at highest supported frequency and make it switch at high rate. E.g. feed at huge register chain with 01 sequence.
Regards,
Frank
not clear what you mean with overload? You can generate a test design with maximal core current consumption by clocking many ("all") logic cells at highest supported frequency and make it switch at high rate. E.g. feed at huge register chain with 01 sequence.
Regards,
Frank
