Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

FPGA configuration time and PCIe secification

Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme? I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interf...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

The 3ms power-on-ramp comes from the hardware design, eg., see p18 of the PDF I just linked to, so that is design-specific, but it is what you must implement when you select msel for fast por, i.e., tramp < 3ms.

--- Quote End ---

Handbook says ( p.11-4 ): "The MSEL pin settings determine the POR time (tPOR) of the device.", but not tRAMP.