FPGA configuration time and PCIe secification

EP4CGX15 and EP4CGX22 ( which I need ) do not support FPP.

EPCS4 cost can fall below 1 USD if M25P40 is used instead. It has the same mfg ID.

The only problem is ( I overlooked it ) is that typical DCLK for AS mode is 33 MHz instead of 40 MHz as I expected.

Maybe its because internal oscillator is used to create the DCLK?

Here is a quote from Handbook:

the dclk generated by the cyclone iv device controls the entire configuration cycle

and provides timing for the serial interface. cyclone iv devices use an internal

oscillator or an external clock source to generate the dclk. for cyclone iv e devices,

you can use a 40-mhz internal oscillator to generate the dclk and for cyclone iv gx

devices you can use a slow clock (20 mhz maximum) or a fast clock

(40 mhz maximum) from the internal oscillator or an external clock from clkusr to

generate the dclk. there are some variations in the internal oscillator frequency

because of the process, voltage, and temperature (pvt) conditions in cyclone iv

devices. the internal oscillator is designed to ensure that its maximum frequency is

guaranteed to meet epcs device specifications. cyclone iv devices offer the option to

select clkusr as the external clock source for dclk. you can change the clock source

option in the quartus ii software in the configuration tab of the device and pin

options dialog box.

That apparently means , that in CLKUSR mode with the stable external clock source for DCLK, the DCLK can be exactly 40MHz.

Did You ever test CLKUSR mode?

If Yes, then what do You think about setting DCLK=40MHz in CLKUSR mode?