FPGA architecture

Hi all,

I'm starting a new project and I need some help with the FPGA architecture. The concept is very simple - the FPGA will sample an input parallel bus (24 or 48 signals @ 150MHz max) and stream it down a PCIe bus. The FPGA will use an external IP for the PCIe bus, combined with Altera's hard IP.

The input bus uses its own clock (meaning that the FPGA is the slave for that matter).

The FPGA will be probably Cyclone IV.

My questions are:

1. Which oscillator frequency should I use for the basic FPGA clock (use a high frequency oscillator or use something like 50MHz and then a PLL to boost it)?

2. How do I make the connection between the FPGA internal clock and the bus clock? For a slow bus clock I would usually register it with 3-4 flip-flops but since this clock is at 150MHz I'm not sure that it the the best solution since I can't oversample it too much.

3. While transferring the data from the FPGA IOs to the PCIe transceiver, is it mandatory to use pipelining? If so what is the best way to do that?

Thank you