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Altera_Forum
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11 years ago

FPGA 2 SDRAM interface

I’m working with the Cyclone V SoC dev kit and I’m trying to get maximum throughput of data from the FPGA to the HPS SDRAM. I’ve been trying to get the fpga2sdram interface working, but I’ve been un...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Just figured out my problem and I thought I'd reply to this to help out people like me out there...

It was the "portdefault" bits in the "protportdefault" SDRAM controller register. They were all set to "1" and not allowing access to the port! I thought this would have been accounted for in the mountain of u-boot code.

I added this to the u-boot.scr after "run bridge_enable_handoff":

mw 0xffc2508c 0;