Found illegal assignment group name conflicts with top-level node name

How to fix the follow errors was appeared after pin assingment (in Pin Planner window) and project compilation:
1) "Error: Found illegal assignment group name "key" -- conflicts with top-level node name";
2) "Error: Found illegal assignment group name "led" -- conflicts with top-level node name".

The errors in Processing tab:

Top-level VHDL:

    library ieee;
    use ieee.std_logic_1164.all;

    entity led_switch is
    port(
        key:in std_logic_vector(9 downto 0);
        led:out std_logic_vector(9 downto 0));
    end led_switch;

    architecture myArc of led_switch is
        signal Y: std_logic_vector(9 downto 0);
    begin

    process(key,Y)
    begin
        Y(0) <= key(0);
        Y(1) <= key(1);
        Y(2) <= key(2);
        Y(3) <= key(3);
        Y(4) <= key(4);
        Y(5) <= key(5);
        Y(6) <= key(6);
        Y(7) <= key(7);
        Y(8) <= key(8);
        Y(9) <= key(9);
        led <= Y;
    end process;

    end myArc;

Pin Planner window:

Also, I did assignments' export in .QSF file:
QSF file (google drive)

I work in Quartus II 9.0 (Build 132 02/25/2009 SJ Web Edition) and use the device Cyclone III (EP3C16F484C6).

What I tried to do already:

1) I attempted to change name of key group (named as "key[9..0]" by default now) on "keyGroup" in Pin Planner window, but after name chaging all the group's pins disappeared (to do it visible again need to execute the command "Refresh" in the View tab of Pin Planner window);

2) Also, I renamed "key" group in "keyGroup" and "led" in "ledGroup". It was did in exported assignments' QSF file. After that, was imported changed QSF file in Quartus, but it did not change situation – the same errors remaided.

But, as soon as I exported changed QSF file, I imported it and got original (before groups' name changing) file. This may indicate the QSF file wasn't exported actually...