Honored ContributorHow do i write for i= 0:63 :360 (matlab code) in VHDL .searched for long about for loops but couldn't see any instance of the above form. Is defining an array and writing "for in A"the only way??
Honored ContributorHonored Contributor@jb123 : I didn't get you
I have to use array values corresponding to those indices(i=0:63:360) M(i ) := blah blahHonored ContributorSorry, but I'm very poor at matlab.
Does your example evaluates in the following: for i = 0, 63, 126, 189, 252, 315 : the loop body is executed i = 378 : the loop is exited Do you have to compare i to 360 instead of 378?Honored Contributorin VHDL, the loop variable is an integer if you use a for loop:
for i in 0 to 63 loop
end loop;
variable i : real : 0.0;
while i < 1.0 loop
....
i := i + 0.001;
end loop;
NB: while loops are not usually synthesisable.
Honored Contributor@jb123 yes that is what i have asked; at few places in my code i have to deal with large integers like 0:64 :10000 , i can't keep giving values; i think i have to create a loop to define a array as such and then gave the array range to the for loop ;
Correct me if I am wrong; @Tricky : How do i use a constraint without using a while loop? any alternative loop which can be synthesisable and serves the purpose??Honored ContributorThe way to start thinking about this - stop thinking about loops and code constructs and think about what the underlying circuit should look like. VHDL stands for VHSIC Hardware Description Language. The key word there is description as VHDL is used for describing a circuit. Without understanding the circuit, how do you expect to write the VHDL?
Matlab -> VHDL is not a straightforward conversion.Honored ContributorOkay. I know what the circuit does. I will be able to write it in vhdl. But can you refer me an article which says synthesisable loops and packages so that i would not commit mistakes again.Please
Thanks for helping me all through thisHonored ContributorFor synthesis, for loops will unroll into parallel hardware. and if you need a while loop you're doing something wrong and clearly dont understand the circuit.
I suggest drawing the circuit out (on paper, or MS visio or similar) before writing any VHDL.
