floating point operating in vhdl (fixed_pkg)

Hi all;

I have write a code using fixed_pkg. It compile successfully in quartus, but when I try to simulate in ModelSim an error occur.

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library ieee;

library ieee_proposed;

use work.fixed_pkg.all;

use ieee.numeric_std.all;

entity fix is

port (clk: in bit;

nprev: in integer range -127 to 127;

ip1: out ufixed (8 downto -9));

end fix;

architecture fix of fix is

signal n1: ufixed (4 downto -4);

begin

process(clk)

begin

if (clk'event and clk='1') then

ip1 <= (to_ufixed(0.483,n1)) * (to_ufixed(11,n1));

end if;

end process;

end fix;

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This is the error in ModelSim:# Compile of fix.vhd failed with 2 errors.# Compile of fix_tb.vhd failed with 2 errors.# Compile of fixed_float_types_c.vhdl was successful.# Compile of fixed_pkg_c.vhdl failed with 1 errors.# Compile of fixed_synth.vhdl failed with 2 errors.

This the error when I expand it:

** Error: H:/altera/mul_try_tb/fix_tb.vhd(2): Library ieee_proposed not found.

I have add all the fixed_pkg in the project (in quartus). Need your helps..