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How should the simulator decide which is the actual input of the flip flop in an RTL simulation?
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VHDL has clear rules for it. Actually, most of the VHDL rules for "order of execution" are only relevant for simulation. In synthesis, logic delays clear most possible doubts, if timing closure can be achieved, everything is fine.
Please notice, that the testbench code
wait until risind_edge(clk);
data <= xxx;
is simply identical to the behavioral code for a register in the data path. So if altfp_div fails with the testbench, it must be expected to fail in functional simulation with a simple register, too. Which means, you can't perform a functional simulation, as the original poster mentioned.
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