--- Quote Start ---
I don't think this is an artifact.
The edge of the clock and the data change simultaneously.
How should the simulator decide which is the actual input of the flip flop in an RTL simulation?
in a timing simulation the situation is different. there you can check for setup and hold times.
I think this is one of the cases in which the result of the simulation depends on the simulator.
In general, letting data and clock edge change at the same time, is asking for trouble.
--- Quote End ---
Well this is actually wrong
The synthesis and clock tree generation will take care of this. Gate level simulation is used to verify the clock tree is buffered correctly and that the design does not brake setup/hold times. Running in max/min corners will assure you don't brake the setup/hold times.
If you would be hand-placing the block into the FPGA then you would use falling->rising edge or to protect your design for metastability between Analog World and FPGA or crossing clock domains...
Honored Contributor
