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I would expect, that Altera is mainly focussing on synthesis performance. I also won't expect issues in the timing analysis.
The latest after Altera abandonned the internal simulator in favor of ModelSim, one should expect simulation proof IP code. Having the timing intentionally set in a test case is only the most obvious case. Normally, the data to altfp_mult would be supplied after rising clock edge from a register burried deep in the code. I guess some experience of the latter kind motivated your tests? So you should file a service request, I'm curious to hear the answer.
In the meanwhile, you could try how many simulation time steps of additional delay in your test bench can make the artefact vanish.
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I don't think this is an artifact.
The edge of the clock and the data change simultaneously.
How should the simulator decide which is the actual input of the flip flop in an RTL simulation?
in a timing simulation the situation is different. there you can check for setup and hold times.
I think this is one of the cases in which the result of the simulation depends on the simulator.
In general, letting data and clock edge change at the same time, is asking for trouble.
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