Floading Point divider, throughput/latency

I would expect, that Altera is mainly focussing on synthesis performance. I also won't expect issues in the timing analysis.

The latest after Altera abandonned the internal simulator in favor of ModelSim, one should expect simulation proof IP code. Having the timing intentionally set in a test case is only the most obvious case. Normally, the data to altfp_mult would be supplied after rising clock edge from a register burried deep in the code. I guess some experience of the latter kind motivated your tests? So you should file a service request, I'm curious to hear the answer.

In the meanwhile, you could try how many simulation time steps of additional delay in your test bench can make the artefact vanish.