Honored Contributor
Honored ContributorHi FvM,
I agree with you and suppose this is due to delta delays in the simulator. I have used simulator resolution 1ps and 1ns with the same resaults. This will then make my design fail in RTL simulation, but work in gatelevel and on the real FPGA... This is fairly annoying and not making me very confident about this... makes me wander if there is something else not done properly. Doing a full simulation on the divider in not realistic as trying all possible inputs will take years in simulation time... How well are those blocks tested by Altera and can I trust them if I have no timing warnings when I verify my design with TimeQuest? Cheers Stefan
