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Hi nplttr,
I'm fully aware of this. My experience is 3 years ASIC design (front-end and back-end design) and ~1 year FPGA design with Altera devices.
In this example when I use the rising edge then the data has a full clock cycle to become stable before it is registered into the divider.
How ever if I use falling edge the data only has half a cycle...
I prefer to keep my design synced on rising edge unless I have a really good reason to switch over to falling edge. To place this buffer into the design will also cost my 64 registers + some additional logic.
I wander if this is a bug in the behavioural code for the divider and if I have to do a gate level simulation for this...
Cheers
Stefan
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You don't have to change the edge of the clock that produces the data.
It will work.
If you want to have an RTL simulation that is consistent with the real device, let the input data change silightly before the edge of the clock that registers it.
Honored Contributor
