Floading Point divider, throughput/latency

Hi nplttr,

I'm fully aware of this. My experience is 3 years ASIC design (front-end and back-end design) and ~1 year FPGA design with Altera devices.

In this example when I use the rising edge then the data has a full clock cycle to become stable before it is registered into the divider.

How ever if I use falling edge the data only has half a cycle...

I prefer to keep my design synced on rising edge unless I have a really good reason to switch over to falling edge. To place this buffer into the design will also cost my 64 registers + some additional logic.

I wander if this is a bug in the behavioural code for the divider and if I have to do a gate level simulation for this...

Cheers

Stefan