Floading Point divider, throughput/latency

In a real system the input for a Flip Flop has to be stable for an interval of time before the active edge of the clock. This time is namd Setup Time (ts) and depends on the technology and the design of the Flip Flop.

In most simulations, it is safe to let the input data change on the falling edge of the clock, if the flip flop is triggered on the rising edge of the clock.

In the real system, the input will be generated by another flip flop with combinational logic.

The relation that has to be verified is the setup constraint that is:

T > tq +Tc.max + ts

Where:

T = Clock period

tq = flip flop delay

ts = setup time

Tc,max = the maximum combinational delay of the logic between the flip flops.