Flex 6000 clock gating

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The gated clock is going only to a pin on the device for an external circuit, and clocks nothing internally. The clock in this legacy design is not fast enough to achieve the external data transfer without a gated clock. I have to change the contents of a data bus every clock cycle, and provide a negative going pulse, midway between data bus changes to transfer the data. Data is not transferred on every clock cycle though, so the pulse needs not to be present some of the time.

I have found now that the gating circuit operates correctly for speed grade 2 (which the design uses) and 3 Flex 6000 devices. I still don't get why the speed grade 1 devices glitch though.

Cheers

Gordon

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Hi,

you have to keep in mind that the speed of an FPGA shows a large varation depending on the temperatur, power supply and the process of production. That means you can not be sure that your design will run with all speed grade 2 devices. If you only need one of your boards it is maybe ok, but you should not use it for a production.

Kind regards

GPK