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Altera_Forum's avatar
Altera_Forum
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16 years ago

fixed point in verilog

hi. I understand that the fixed point in verilog is represented by signed [4:-2] where -2(2 bit for post binary point) is for tracking purpose. Pls correct me if i am wrong.

However, i have no idea on how to use in verilog for any arithmetic operation.

e.g.

module fixed_point_addition

(dataA, dataB, result_add, result_mult);

input signed [3:-1] dataA;

input signed [3:-1] dataB;

output signed [4:-2] result, result_mult;

assign result_add = dataA + dataB;

assign result_mult = dataA* dataB;

endmodule

In waveform editor, i cant set the value like 3.5. How to do this?

i set the input(dataA=0.5 and dataB=0.5) and output in fraction when performing simulation, the result(result_mult= 0.125). May i know the reason?

Can i have some simple source code in verilog(can perform 3.25 * -6.125) and how to perform the simulation?

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Verilog does not have special support for fixed point arithmetic. Using negative indexes is a nice way to remember how many fractional bits you have, but Verilog does not track it for you.

    Since your inputs have only 1 fractional bit, your resolution is 0.5. You can't represent 3.25 or -6.125. You can only represent 3.0 or 3.5 or -6.0 and -6.5.

    Aditionally, your output has 2 fractional bits. That is why you're seeing half of what you expect.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You can use a scaling factor of 4 respectively 0.25 according to your 2 fractional bits. Isn't it obvious?