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kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Fitting failed on agilex7 40Gbe MAC hard ip

Hello

I'am trying to compile the example design generated by quartus 24.1 - MAC 40Gbe hard IP

i received the following fitting Error :

Error(22241): Cannot place the block u_eth_f_hw|IP_INST[0].hw_ip_top|dut|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx at location fgt_q0_ch0_rx because it uses port next_bonding_link that is not present at this location.

The 156.25Mhz reference clock is connected to i_refclk2pll port of the example design and is connected : to PIN_BV13

The RX and TX pins are connected to :

set_location_assignment PIN_BJ10 -to FGTL13A_TX_Q0_CH0p -comment IOBANK_13A
set_location_assignment PIN_BK11 -to FGTL13A_TX_Q0_CH0n -comment IOBANK_13A
set_location_assignment PIN_BM7 -to FGTL13A_TX_Q0_CH1p -comment IOBANK_13A
set_location_assignment PIN_BL8 -to FGTL13A_TX_Q0_CH1n -comment IOBANK_13A
set_location_assignment PIN_BN10 -to FGTL13A_TX_Q0_CH2p -comment IOBANK_13A
set_location_assignment PIN_BP11 -to FGTL13A_TX_Q0_CH2n -comment IOBANK_13A
set_location_assignment PIN_BT7 -to FGTL13A_TX_Q0_CH3p -comment IOBANK_13A
set_location_assignment PIN_BR8 -to FGTL13A_TX_Q0_CH3n -comment IOBANK_13A

set_location_assignment PIN_BM1 -to FGTL13A_RX_Q0_CH0p -comment IOBANK_13A
set_location_assignment PIN_BL2 -to FGTL13A_RX_Q0_CH0n -comment IOBANK_13A
set_location_assignment PIN_BN4 -to FGTL13A_RX_Q0_CH1p -comment IOBANK_13A
set_location_assignment PIN_BP5 -to FGTL13A_RX_Q0_CH1n -comment IOBANK_13A
set_location_assignment PIN_BT1 -to FGTL13A_RX_Q0_CH2p -comment IOBANK_13A
set_location_assignment PIN_BR2 -to FGTL13A_RX_Q0_CH2n -comment IOBANK_13A
set_location_assignment PIN_BU4 -to FGTL13A_RX_Q0_CH3p -comment IOBANK_13A
set_location_assignment PIN_BV5 -to FGTL13A_RX_Q0_CH3n -comment IOBANK_13A


Any help ?

Thx

Configuration
Generic Io
Other Ips
  • kikoss's avatar
    kikoss
    1 year ago

    Seems that should check appropriate pinout following restriction in the altera tool :

    f-tile-channel-placement-tool.xlsx


5 Replies

  • kikoss's avatar
    kikoss
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Seems that should check appropriate pinout following restriction in the altera tool :

    f-tile-channel-placement-tool.xlsx


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

    Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

    Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.


    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Did your issue has been resolved after using f-tile channel toolkit?


    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Since no hear any feedback from you, I am now close the case. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Best regards,

    zying


  • kikoss's avatar
    kikoss
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hello I already write the solution , and accept it

    Thank you very much