--- Quote Start ---
Without the code, we have no idea what could be the problem.
Is it some large unpipelined logic design with feedback?
Post the code so we can at least start to speculate.
--- Quote End ---
Her is may be the part of problem:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.AES_package.all;
entity Expand is
port(
clk,reset : in std_logic;
opsel : in std_logic;
keylen : in std_logic_vector( 1 downto 0);
Cipherkey : in c256key_type;
RoundkeyArray : out RoundkeyArray_type
);
end entity Expand;
architecture Struct of Expand is
----------------------------------------------------
component C128RndkyGen is
port(
Round_index : natural range 0 to 10;
Roundkey_in : in c256key_type;
Roundkey_out : out c256key_type
);
end component C128RndkyGen;
----------------------------------------------------
component InvMixRndky is
port(
clk,reset :in std_logic;
Roundkey_in : in Roundkey_type;
Roundkey_out : out Roundkey_type
);
end component InvMixRndky;
----------------------------------------------------
signal control: std_logic_vector(2 downto 0);
signal CREG,CNXT : natural range 0 to 10:=10;
signal TRKA192 :Roundkey256Array_type;
signal RIN,RREG,RNXT,ROUT128,ROUT192,Rout256 :c256key_type;
signal FRKA,RKA128,FRKA128,DRKA128,RKA192,FRKA192,DRKA192,RKA256,FRKA256,DRKA256 :RoundkeyArray_type;
signal Cipherkey_reg : c256key_type;
begin
process (clk ,reset)
begin
if reset='0' then
Cipherkey_reg <= (others => (others => x"00"));
RREG <= (others => (others => x"00"));
CREG <= 0;
elsif (clk'event and clk='1') then
Cipherkey_reg <= Cipherkey;
RREG <= RNXT;
CREG <= CNXT;
end if;
end process;
---Common Resources
control <= opsel & keylen;
-- INPUT MUX
RIN <= Cipherkey_reg WHEN CREG=1 ELSE RREG;
--MUX1
WITH KEYLEN SELECT
RNXT <= ROUT128 WHEN "00",
ROUT192 WHEN "01",
ROUT256 WHEN "10",
(others => (others => x"00")) WHEN OTHERS;
--THE COUNTER combinational circuit
CNXT <= 1 WHEN CREG=10
ELSE CREG+1;
RKA128(1) <= ( 1=>Cipherkey_reg(1), 2=>Cipherkey_reg(2), 3=>Cipherkey_reg(3), 4=>Cipherkey_reg(4));
Rndky128Gen : C128RndkyGen
port map(
Round_index => CREG
,Roundkey_in => RIN
,Roundkey_out => ROUT128
);
process(CREG)
begin
case CREG is
when 1 =>
RKA128(11) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 2 =>
RKA128(2) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 3 =>
RKA128(3) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 4 =>
RKA128(4) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 5 =>
RKA128(5) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 6 =>
RKA128(6) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 7 =>
RKA128(7) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 8 =>
RKA128(8) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 9 =>
RKA128(9) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when 10 =>
RKA128(10) <= (1=>ROUT128(1),2=>ROUT128(2),3=>ROUT128(3),4=>ROUT128(4));
when others =>
null;
end case;
end process;
end architecture;
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