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Altera_Forum
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15 years ago

Fitter ignoring PLL compensation assignment as invalid

Hi all, Fitter ignoring PLL compensation (source synchronous mode) assignment as invalid. Any ideas as to why this may be happening? I am using Quartus v 10.1
Altera_Forum's avatar
Altera_Forum
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15 years ago

Can you be a little more specific, and provide some more detail? In source synchronous mode, the PLL compensates the clock so that the clock-data relationship at the pins of the device is maintained at the input register (assuming you don't add any -offset or -phase adjustments to the PLL output clock.)