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alperenpalp's avatar
alperenpalp
Icon for New Contributor rankNew Contributor
5 years ago
Solved

FIR II core IP outputs incorrect data.

Hello, It's my first time using intel's FIR filter IP and I'm having difficulties getting it working. I basically want to low-pass filter the data coming from the ADC (LTC2387) using FIR II IP. T...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,

    Would you mind to help opening a new thread on this. Thank you very much.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Regarding your latest inquiry on the clock rate vs sample rate, for your information, you can refer to the "Figure 13. Time-Division Multiplexing to Save Hardware Resources" in the FIR II IP Core User Guide for further details. You would need to code additional logic on your own for the serializer and deserializer to work with the FIR II IP. When you are having higher clock rate than sample rate, you are trying to save resource required for FIR II IP.


For example, in your case of 50MSPS and clock rate 100MHz, the FIR II IP is expecting that your serializer will serialize two data stream of 50MSPS into single data stream of 100MSPS. If you do not have the serializer and assert source_valid at 25MSPS, then you should observe your output at 25MSPS.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


alperenpalp's avatar
alperenpalp
Icon for New Contributor rankNew Contributor
5 years ago

Thanks for your response,

I am going to get back to this, but before I do let me ask you a quick question. As you can seen in my latest screen shot I left the sink_valid signal at all times and yet I still see the source_valid signal asserted at 25 MSPS. I don't understand how it is expected.

Does the IP assume that I am feeding 2 channels when I use 2 time higher clock rate?

Thank you for being patient with me.