New ContributorHi,
Would you mind to help opening a new thread on this. Thank you very much.
Regular ContributorHi,
Your understanding is correct. In my example simulation, the valid signal is high all the time. This example is to show working simulation and for reference only. It is not matching your test bench directly.
I am using Q17.0Std to create the example. I believe you are using QPro edition. If yes, you can use the IP Parameter Editor Pro to generate the Testbench System for your FIR II IP, and then customize from there. You may refer to my example on some of the changes required to the test bench to enable simulation.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHello,
I am using quartus prime lite 19.1 edition.
I am able to reproduce the results that you shared, but I am just more confused (sorry for this I am kind of new to using quartus).
My first question is the rate of the output I am seeing the output data at 7.5MSPS which matches your results. THe IP is configured to be 15 MSPS. Isn't it wrong? SHouldn't we get 15 MSPS output rate?
Secondly, I don't understand how to represent the output data. The output data is 38 bits and I want to know how to make use of it? I expect the output to be 8100h after it settles, but the output data makes no sense to me. How do I represent the data?
Regular ContributorHi,
Sorry if there is any confusion. Let's move to the basic mode of the FIR to ease the discussion. Then you can further customize from there.
I have create a test design with Clock Rate = Sample Rate. Then, input a pulse to the FIR IP. From the simulation, you can see the FIR output each of the coefficient in sequence which is an expected behavior. Attached is the test.zip with simulation files for your reference. You can try out on your side to verify the FIR behavior. Then, you can try with your own data.
Note that I am not sure about what should be the expected output with your input 0x8100. But after verifying the FIR is working fine with pulse, the output of the simulation should be correct. In my Modelsim simulation, I am setting the radix of my source_data = sfixed.
Please let me know if there is any concern. Thank you.
New ContributorOK I think I understand it now.
I am sorry for bothering you with very basic questions, but I am kind of new to signal proccessing, so take it wasy on me.
I was expecting to the output value after the filter settles. I learnt about "filter gain" and now I am not confused about the output value anymore.
I got a different confusion right now. It's about "clock rate" and "input sample rate". When I set them equal i.e 100MHz clock rate and 100 MSPS samples rate I got no problem. I get the expected value for each cycle of the clock. When I set the sample rate different, let's say 50MHz, I get always get the output at half of the input sample rate.
I attached an example or you can take a look at the screenshot. source_valid is asserted at a rate of 25MSPS.
What am I missing here?
If you want to load the modelsim example the test bench is FIR_tb and qsys file is unsaved.qsys from there you can see the configurations, and you can open the project "FIR_filter_test.mpf" I am directly using the synthesis files for the simulation.
Thanks for bearing with me.
