New ContributorHi,
Would you mind to help opening a new thread on this. Thank you very much.
Regular ContributorHi,
Sorry for the delay. As I understand it, you observe some issue with the FIR II IP. If I understand it correctly, you are observing it in simulation. To ensure we are on the same page, would you mind to share with me a simple Modelsim simulation example together with steps which could replicate your observation? Some screenshots to further elaborate on the issue would be very helpful. Thank you very much.
New ContributorHello,
Thank you for your answer,
I am observing the output of the FIR filter (FIR filter output (36 bit data)) in signal tap, so it's not modelsim simulation, it's real hardware implementation. Signal Tap file is also included in the .qar file that I shared.
I understand that the file I shared is kind of complicated it's a portion of our design we working on I am sorry for its messiness. I kindly ask you to inspect pre_process IP. I t includes the FIR filter and data conversion(2's complement to bit magnitude conversion for the input).
This is my understanding on how the IP works:
I only need a signle channel therefore the error signals kind of irrelevant (no SOP or EOP), therefore I ignored them left them 'open' in the VHDL file. Sink side has an error input I don't know what to do with that. The input is 16-bit signed binary, I assume this bit magnitude form where the first bit is the sign and the rest is the number. The input 15MSPS, the output 20MSPS, the clock to the filter is 60MHz. What I do is I fixed the input signal at 0x8100 and assert sink valid at every 4th(60MHz/15MSPS = 4) cycle of the clock and expect the source valid to be asserted at every third cycle of the clock which is what we see in the waveform that I attached, but the output looks completely random.
What am I doing wrong?
