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For starters we will be impleming one core as a proof of concept so the 1GbE is entirely sufficient however once that is running we were hoping to make multiple cores. the 1GbE will limit us to 8 cores before we run into data starvation. Ideally we would like more than 8 cores which is why we were looking to explore other options.
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I would recommend ignoring the limitation of 1GbE, and talk with your advisor about the following option;
1. You implement the 8 cores and show that the system works, and that 1GbE is sufficient.
2. You implement more cores in the FPGA, and allow the 1GbE interface to select a subset of 8 cores.
At that point you will have shown that your FPGA resources are sufficient to implement +8 cores, but due to interface issues, you cannot stream more than 8 cores.
Don't bother getting distracted by the Cypress chip at that time. I won't of course take my own advice, and will get distracted by it ... :)
Cheers,
Dave
Honored Contributor
