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Altera_Forum
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14 years ago

FIFOed UART BSP errors

Hello,

I am trying to use the FIFOed UART for Nios rev 9.3 and have instantiated the module successfully in SOPC builder. I generated SOPC and compiled Quartus successfully. I am trying to install the software components, but do not have the "Custom Components Search Path" button in the BSP Editor under tools/options and "BSP Component Search Paths" as mentioned in the FIFOed_Avalon_UART_v9.30.doc document.

I am running Quartus version 10.1 software.

When I build the BSP project and my Hello World project, I get the following errors:

**** Build of configuration Nios II for project hello_world_1 ****

make all

Info: Building ../hello_world_1_bsp

make --no-print-directory -C ../hello_world_1_bsp

[BSP build complete]

Info: Linking hello_world_1.elf

nios2-elf-g++ -T'../hello_world_1_bsp/linker.x' -msys-crt0='../hello_world_1_bsp/obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../hello_world_1_bsp -Wl,-Map=hello_world_1.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mhw-mulx -o hello_world_1.elf obj/CWM_Main.o obj/Cal.o obj/DataLink.o obj/dual_port_ram.o obj/elapsed_time_recorder.o obj/reg_io.o obj/temp_sensor.o -lm

../hello_world_1_bsp\libhal_bsp.a(alt_sys_init.o): In function `alt_sys_init':

c:/altera/cwm_dig_ctrl/quartus/software/hello_world_1_bsp/alt_sys_init.c:115: undefined reference to `fifoed_avalon_uart_init'

../hello_world_1_bsp\libhal_bsp.a(alt_sys_init.o):(.data+0x1138): undefined reference to `fifoed_avalon_uart_read_fd'

../hello_world_1_bsp\libhal_bsp.a(alt_sys_init.o):(.data+0x113c): undefined reference to `fifoed_avalon_uart_write_fd'

collect2: ld returned 1 exit status

make: *** [hello_world_1.elf] Error 1

Does anyone know how to resolve these errors and install the software driver without the "Custom Components Search Path" button in BSP Editor?

Thanks.

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    have you included the right file ?

    # include "fifoed_avalon_uart_regs.h"

    and used the corresponding functions ?

    IORD_FIFOED_AVALON_UART_TXDATA(base)

    IOWR_FIFOED_AVALON_UART_TXDATA(base, data)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    So in my main.c I should add the

    # include "fifoed_avalon_uart_regs.h"

    ?

    I am not using the corresponding functions:

    IORD_FIFOED_AVALON_UART_TXDATA(base)

    IOWR_FIFOED_AVALON_UART_TXDATA(base, data)

    I'll have to recompile and give it a try.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    you have to defined functions, registers, ...

    I use altera IO function so I have included this file.

    # include "fifoed_avalon_uart_regs.h"

    an example to use the fifoeduart (read/write) :

    void WriteCharUART(alt_u8 ch)

    {

    IOWR_FIFOED_AVALON_UART_TXDATA(USB_FIFO_UART_BASE,ch);

    while (!(IORD_FIFOED_AVALON_UART_STATUS(USB_FIFO_UART_BASE) & 0x0040)); // while trdy==0

    }

    void WriteSentenceUART(char* text)

    {

    int temp = 0;

    while (text[temp] != '\0')

    {

    WriteCharUART(text[temp]);

    temp++;

    if (temp == 100)

    return;

    }

    }

    void handle_io_uart_interrupts(void* context, alt_u32 id)

    {

    char tmp_buff;

    // you can use "context" as a parameter

    tmp_buff = IORD_FIFOED_AVALON_UART_RXDATA(USB_FIFO_UART_BASE);

    if (tmp_buff>=0x20)

    printf("| %c ", tmp_buff);

    else

    printf("| 0x%X ", tmp_buff);

    }

    int main()

    {

    int ctrl;

    // IRQ off

    IOWR_FIFOED_AVALON_UART_CONTROL(USB_FIFO_UART_BASE, 0);

    // init program

    …

    // init uart

    IOWR_FIFOED_AVALON_UART_CONTROL(USB_FIFO_UART_BASE, 128); // Enable interrupt for a read ready = caractere receive

    alt_irq_register(USB_FIFO_UART_IRQ, (void *)&ctrl, handle_io_uart_interrupts);

    while (1)

    {

    }

    return 0;

    }
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I was able to get the Eclipse project build to work finally and run the configuration on my Nios hardware. We are currently not receiving all of the bytes expected, but are looking into this. I'll let you know if we have any other issues.

    Thanks for your help.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I was able to get the FIFOed UART to work properly and am now able to send data across at 1 Mbps. Thanks for your help!

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi

    I'm having trouble with the FIFOed avalon uart. It "generates" in SOPC, compiles in project but I'm not getting any interaction from it using altera uart drivers.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Equinox,

    I don't know what can be your problem.

    I have used the example code above and it was working well with my hardware: pc hyperterminal <-> ftdi chip <-> nios with fifoed uart.

    maybe read again the documentation:

    http://www.alterawiki.com/wiki/fifoed_avalon_uart

    set the same rate at both side of the uart and try first a slow rate.

    If it still doesn't work you can try to instantiate 2 uarts in a nios then connect them together (uart1_rx<->uart2_tx / uart1_tx<->uart2_rx).

    Then in a nios software project try to send data and receive data, maybe only a simple char first.

    It will help you to understand how it works.

    good luck.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hey Fates,

    I've further debugged my issue with some help from a senior.

    There seems to be a bug with setting the divisor for the fifoed uart.

    for example if I want 115200 baud rate the divisor would be 174 but instead 01740174 is there.

    using regtools i can set it to be 00000174.

    currently debugging to see what is the cause.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    FWIW don't use hyperterminal - it has a nasty habit of looking at the modem control signals.

    putty works a lot better (and as a linux X program).

    The duplicated data might have something to do with byte enables, and/or bus width adapters.