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Altera_Forum's avatar
Altera_Forum
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16 years ago

FIFO read problem

Dear All, I have instantiated an Async FIFO. An external USB controller chip writes to the write port of the FIFO and I plan to read the data from the read port to use further in my design insi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

To debug first generate the count values from an internal counter running on wr clk.

Write enable to be high always. Rd enable to be high after write by few clks.

in signaltap look at fifo input data and output data directly(no intermediate registers). use proper clk for signaltap(as wr or rd clk whichever is faster, or use clk faster than both).

To avoid signaltap problems, you may just read back internally and compare data to another running count, producing a flag on led or in signaltap