Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

FIFO read problem

Dear All,

I have instantiated an Async FIFO. An external USB controller chip writes to the write port of the FIFO and I plan to read the data from the read port to use further in my design inside the Cyclone II FPGA.

I have brought all the FIFO signals to the SignalTapII LA. To test my code, I transmit an incrementing counter from the USB controller chip. On the SignalTap screen I observe that the write port is presented with proper input (increasing counter) and proper write request. At the read port, I receive the data and most of the values seem to increment (which is correct), but at many read requests, two or more ( I have seen 4) values are the same i.e. the same value is read multiple times. And at some other read requests, the counter decrements (like reading the FIFO reverse order). Neither of these situations have any other signal activities (i.e. there is no assertion and de-assertion of the empty or full signals).

I'm confused. Can any one of you throw light into the problem?

Nagaraj

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    To debug first generate the count values from an internal counter running on wr clk.

    Write enable to be high always. Rd enable to be high after write by few clks.

    in signaltap look at fifo input data and output data directly(no intermediate registers). use proper clk for signaltap(as wr or rd clk whichever is faster, or use clk faster than both).

    To avoid signaltap problems, you may just read back internally and compare data to another running count, producing a flag on led or in signaltap