FIFO and DMA configuration

Hi, I want to send a 192 bit wide stream of data from IO pins to the SDRAM using a FIFO and DMA configuration. is it a sensible solution (or even possible) to use the A-ST DC FIFO with '64 bits pr symbol' and '3 symbols pr beat', and a SGDMA with 64bit width to read from the FIFO.

im also wondering if the A-ST FIFO is made using on-chip memory blocks, i guess they are but i havent found it in the datasheets.