Fault Injection on Stratix V via JTAG interface

I'm trying to inject a fault onto the CRAM of a Stratix V FPGA. From reading AN-539 and Chapter 9 "SEU Mitigation for Stratix V Devices" of the Stratix V handbook I gathered the following information:

A) - Internal scrubbing and detection can be activated in the menu given in Device > Device and Pin Options > Error Detection CRC (tab) by ticking the "Enable Error Detection CRC_ERROR pin", "Enable open drain on CRC_ERROR pin" and "Enable internal scrubbing".

B) - Fault injection for simulation of a SEU and consequent corruption of the CRAM can be performed:

i) through the interface provided by the "Altera Fault Injection" in conjunction with the "Altera Error Message Register Unloader" IP cores

ii) through the JTAG interface

I want to be able to use ii). Is there still the need to instantiate the Altera Fault Injection IP as well? There is no explicit information regarding this. From what I gather, it suffices to activate the options in A).

Is this true?

I have no interest in introducing User Mode Detection on my project, only to signal the CRC error occurrence through a pin of the FPGA. In this case, using only the JTAG interface to simulate a SEU of single-bit corruption, as given in the Example 5 .jam file in AN-539 suffices to ensure the correct propagation of the CRC_ERROR signal to the interface to where it connects.