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Honored Contributor
Honored ContributorFault Injection on Stratix V via JTAG interface
I'm trying to inject a fault onto the CRAM of a Stratix V FPGA. From reading AN-539 and Chapter 9 "SEU Mitigation for Stratix V Devices" of the Stratix V handbook I gathered the following information...
Altera_ForumHonored Contributor
Honored Contributorthe error injection with cycloneV works. I used:
..\15.1\quartus\bin64\quartus_jli.exe -aerror_inject -c1 error_inject.jam with jam File from AN-539. Please note that the CRC_Error Pin pulses in my case every 4s for 4ms. This depends on the "Divide error check frequency"
